1. Field of the Invention
The present invention relates to a cache controller, a method for controlling the cache controller, and a computing system comprising the same. More particularly, the present invention relates to a cache controller, a method for controlling the cache controller, and a computing system that separate instruction and data in a unified cache.
2. Descriptions of the Related Art
Cache plays an important role in the modern CPU design. A cache is used to store a small portion of content that are frequently accessed and reused by a CPU. If the stored content have temporal and spatial locality, a cache can be efficiently accessed. Content to be stored in cache comprises instructions and data. Most instructions have locality between each other and most data have locality between each other; however there is no locality between an instruction and data.
Caches can be generally classified into unified caches and non-unified caches. In a non-unified cache, instructions and data are dealt separately. Specifically, a non-unified cache stores instructions and data in different hardware and has two ports for transmitting instructions and data individually. Since instructions and data are dealt separately, it is easy to maintain the locality between the instructions stored in the cache and the locality between the data stored in the cache.
On the contrary, a unified cache stores instruction and data in same hardware and uses a single port for transmitting both instructions and data. FIG. 1 illustrates a schematic view of a conventional computer system 1 using a unified cache. The computer system 1 comprises a processor 11, a unified cache controller 13, and a memory module 15. Moreover, the unified cache controller 13 comprises a cache 131.
The unified cache controller 13 is connected to the processor 11 via a first port 130, a second port 132, and a third port 134. The first port is configured to receive an address of a content from the processor 11, wherein the content may be instructions or data. The second port 132 is a dummy port in the conventional unified cache controller 13. The third port 134 is configured to transmit content of the cache controller 13 to the processor. Apparently, data and instructions are mixed in the cache 131 and the cache controller 13 has no way to manage the content stored in the cache 131. Specifically, when the cache lines are full, the cache controller 23 just flushes one or more cache lines without regarding the content stored in the flushed cache lines. Therefore, it is possible that the cache controller 23 flushes an instruction or data that will be used in the next cycle, which will increase the probability of cache miss.
Unified caches are popular in the modern CPU design because they can be designed and expanded easily. Therefore, it is urgent to find an approach for the unified cache to solve the problem of high cache miss causing by the competition of instructions and data.